1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits and, more particularly, to circuits and methods for dual-gated transistors.
2. State of the Art
Leakage current is a significant concern and problem in low-voltage and low-power battery-operated CMOS circuits and systems, and particularly in dynamic random access memories (DRAMs). As shown in FIG. 1, if low voltages are used for low-power operation of electronic circuits or devices, then a problem exists with threshold voltages and standby leakage current. To get significant overdrive and reasonable switching speeds, the threshold voltage magnitudes must be small, even near zero volts. However, when such small threshold voltages are used, the transistor will have a large sub-threshold leakage current. Various techniques have been employed to allow low-voltage operation with CMOS transistors that can have a relatively large variation in threshold voltage, but yet have low sub-threshold leakage currents in a standby state. Gate body-connected CMOS transistors in vertical device structures provide a dynamic or changing threshold voltage, i.e., lower threshold voltage when the transistor is on and a higher threshold voltage when the vertical transistor is off.
Transistors in CMOS circuits, and in particular CMOS circuits in semiconductor memories, are subjected to continuous reduction in dimensions to accommodate increasing transistor densities. It is known that semiconductor memories, comprised of CMOS circuits, are widely used in computer systems for storing data. A DRAM memory cell typically includes an access field-effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. The data charges on the storage capacitor are periodically refreshed during a refresh operation.
Memory density is typically limited by a minimum lithographic feature size (F) that is imposed by lithographic processes used during fabrication. For example, one generation of high-density dynamic random access memories (DRAMs), which are capable of storing 512 Megabits of data, require an area of 4 F2 per bit of data. There is a need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs. Increasing the data storage capacity of semiconductor memories requires a reduction in the size of the access transistor and storage capacitor of each memory cell. However, other factors, such as sub-threshold leakage currents, require attention in order to lower the overall power consumed by the integrated circuits. There is also a need in the broader integrated circuit art for dense structures and fabrication techniques.